Field of the Invention
Embodiments of the present invention relate to a liquid crystal display (LCD) device. And more particularly, the embodiments of the present invention relate to an LCD device with an oxide thin film transistor which is adapted to prevent a short defect between signal lines within a pad portion area of a display panel.
Description of the Related Art
In general, an LCD device displays images by controlling light transmittance of liquid crystal with dielectric anisotropy using an electric field. Such an LCD device includes a color filter substrate and a thin film transistor array substrate combined with having a liquid crystal layer therebetween. The color filter substrate is provided with a color filter array, and the thin film transistor array substrate is provided with a thin film transistor array.
In order to improve a narrow viewing angle of the LCD device, a variety of new modes applicable to the LCD device are being researched and developed. In accordance therewith, LCD devices being driven in one of an in-plane switching (IPS) mode, an optically compensated birefringence (OCB) mode, a fringe field switching (FFS) mode and so on, are being used as wide viewing angle LCD devices.
Among the wide viewing angle LCD devices, the IPS mode LCD device enables a lateral electric field to be generated between a pixel electrode and a common electrode which are arranged on the same substrate. As such, major axes of liquid crystal molecules are aligned along a lateral direction parallel to the substrate. In accordance therewith, the IPS mode LCD device can provide a wider viewing angle compared to a twisted nematic (TN) mode LCD device of the related art.
FIG. 1 is a planar view showing an LCD device of the related art. FIG. 2 is a cross-sectional view largely showing a region A in FIG. 1.
Referring to FIGS. 1 and 2, the related art LCD device is defined into a display area DA and a pad area PDA surrounding the display area DA. The display area DA can be defined into a plurality of pixel regions PX.
The pixel regions PX can be defined by pluralities of gate lines GL and data lines DL crossing each other. Also, thin film transistors are disposed at intersections of the gate lines GL and the data lines DL. Moreover, a pixel electrode and a common electrode are disposed in each of the pixel regions PX.
Meanwhile, a gate pad portion GPP and a data pad portion DPP are disposed in the pad area PDA. The gate pad portion GPP and the data pad portion DPP is used to receive gate driving voltages and data voltages from an external system.
Such gate and data pad portions GPP and DPP each include a plurality of pads. The plural pads of the gate pad portion GPP and the plural pads of the data pad portion DPP can be connected to ends of the gate lines GL and the data lines DL which are arranged in the display area DA.
To this end, not only gate link lines are arranged between the gate pad portion GPP and the gate line GL on the display area DA but also data link lines are arranged between the data pad portion DPP and the data lines DL on the display area DA. The gate link lines can be formed either in a single body united with the respective gate line GL or in a different layer from the respective gate line GL. The data link lines can be formed in the same shape as the gate link lines.
Referring to FIG. 2, a gate link line 11 is disposed in the pad area PDA of a substrate 10. The gate link line 11 is formed in the same layer as the respective gate line GL which are arranged on the display area DA of the substrate 10. Also, common voltage lines 21 are arranged above the gate link line 11 in such a manner as to cross the gate link line with having a gate insulation film 12 and an interlayer insulation film 13. Moreover, a first passivation film 14, a planarization film 15 and a second passivation film 16 are sequentially formed on the substrate 10 provided with the common voltage lines 21.
However, a foreign substance P can be stained on the gate link line 11. In this case, a fault pattern can be generated when the gate insulation film 12 and the interlayer insulation film 13 are formed on the substrate 10 stained with the foreign substance P. In other words, the fault pattern can be generated by the foreign substance P during depositions of the gate insulation film 12 and the interlayer insulation film 13.
Such a fault pattern can cause a short defect to be generated between the gate link line 11 and the common voltage line 21.
Also, although the short defect due to the foreign substance P is not generated, an abnormal electric potential can be generated between the common voltage line 21 and the gate link line 11 within a region in which the foreign substance P exists. Due to this, signal distortion can be caused by the foreign substance P.